External interrupt limitation due to the NVIC

Hi guys,

I was discussing with my colleagues the problem of the NVIC multiplexer within the STm32 (and probably every CortexM) that limits the number of external interrupts.
For example, EXTI1_IRQHandler can be triggered by any pin Px.1 (mutually exclusive) among the available ports, a limitation is therefore that you cannot enable an interrupt simultaneously on PA.1 and PB.1.
Then came Espruino into the discussion, and we wondered how is it possible to do a setWatch on PA.1 in addition to another setWatch on pin PB.1?
If possible, what is the trick? Does Espruino poll the inputs and generate virtual interrupts?

My understanding was PA.1 and PA.2 is fine but not PA.1 and PB.1 . Thats how i understand the 2. Note in the setWatch reference.

whoops sorry, you're right. Corrected :-)

Well thanks for pointing the note in the setWatchreference ! That's a good answer.
It seems that this limitation can't be bypassed :-/

This would be my guess too, since its hardware related. Maybe you could add some layer on top of it, like you mentioned with polling, but i imagine this would come at a hefty price speedwise.

Yes, I'm not sure if it can be worked around :(

It's not specific to the Cortex M because the Nordic chips don't have the limitation (you can attach an interrupt to any pin - but then you have less interrupts in total). While STM32F1/F4 have the issue I wonder whether maybe some other ST devices don't.