Pins that don't play well together

I'm not quite sure I understand what you mean about the extra bits being set? Could you give me an example with analogWrite(A8) and peek?

The code here appears to be taking the first timer in the list of available timers: https://github.com/espruino/Espruino/blob/master/targets/stm32/jshardware.c#L1532

And the gen/jspininfo.c file looks like:

/* PA0  */ { JSH_PORTA, JSH_PIN0, JSH_ANALOG123|JSH_ANALOG_CH0, { JSH_AF0|JSH_TIMER5|JSH_TIMER_CH1, 0, 0, 0 } },
/* PA1  */ { JSH_PORTA, JSH_PIN1, JSH_ANALOG123|JSH_ANALOG_CH1, { JSH_AF0|JSH_TIMER2|JSH_TIMER_CH2, JSH_AF0|JSH_TIMER5|JSH_TIMER_CH2, 0, 0 } },
/* PA2  */ { JSH_PORTA, JSH_PIN2, JSH_ANALOG123|JSH_ANALOG_CH2, { JSH_AF0|JSH_TIMER2|JSH_TIMER_CH3, JSH_AF0|JSH_TIMER5|JSH_TIMER_CH3, JSH_AF0|JSH_USART2|JSH_USART_TX, 0 } },
/* PA3  */ { JSH_PORTA, JSH_PIN3, JSH_ANALOG123|JSH_ANALOG_CH3, { JSH_AF0|JSH_USART2|JSH_USART_RX, JSH_AF0|JSH_TIMER5|JSH_TIMER_CH4, JSH_AF0|JSH_TIMER2|JSH_TIMER_CH4, 0 } },
/* PA4  */ { JSH_PORTA, JSH_PIN4, JSH_ANALOG12|JSH_ANALOG_CH4, { JSH_AF0|JSH_DAC|JSH_DAC_CH1, 0, 0, 0 } },
/* PA5  */ { JSH_PORTA, JSH_PIN5, JSH_ANALOG12|JSH_ANALOG_CH5, { JSH_AF0|JSH_DAC|JSH_DAC_CH2, JSH_AF0|JSH_SPI1|JSH_SPI_SCK, 0, 0 } },
/* PA6  */ { JSH_PORTA, JSH_PIN6, JSH_ANALOG12|JSH_ANALOG_CH6, { JSH_AF0|JSH_TIMER3|JSH_TIMER_CH1, JSH_AF0|JSH_SPI1|JSH_SPI_MISO, 0, 0 } },
/* PA7  */ { JSH_PORTA, JSH_PIN7, JSH_ANALOG12|JSH_ANALOG_CH7, { JSH_AF0|JSH_TIMER8|JSH_TIMER_CH1|JSH_TIMER_NEGATED, JSH_AF0|JSH_TIMER3|JSH_TIMER_CH2, JSH_AF1|JSH_TIMER1|JSH_TIMER_CH1|JSH_TIMER_NEGATED, JSH_AF0|JSH_SPI1|JSH_SPI_MOSI } },
/* PA8  */ { JSH_PORTA, JSH_PIN8, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER1|JSH_TIMER_CH1, 0, 0, 0 } },
/* PA9  */ { JSH_PORTA, JSH_PIN9, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART1|JSH_USART_TX, JSH_AF0|JSH_TIMER1|JSH_TIMER_CH2, 0, 0 } },
/* PA10 */ { JSH_PORTA, JSH_PIN10, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART1|JSH_USART_RX, JSH_AF0|JSH_TIMER1|JSH_TIMER_CH3, 0, 0 } },
/* PA11 */ { JSH_PORTA, JSH_PIN11, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER1|JSH_TIMER_CH4, 0, 0, 0 } },
/* PA12 */ { JSH_PORTA, JSH_PIN12, JSH_ANALOG_NONE, { 0, 0, 0, 0 } },
/* PA13 */ { JSH_PORTA, JSH_PIN13, JSH_ANALOG_NONE, { 0, 0, 0, 0 } },
/* PA14 */ { JSH_PORTA, JSH_PIN14, JSH_ANALOG_NONE, { 0, 0, 0, 0 } },
/* PA15 */ { JSH_PORTA, JSH_PIN15, JSH_ANALOG_NONE, { 0, 0, 0, 0 } },
/* PB0  */ { JSH_PORTB, JSH_PIN0, JSH_ANALOG12|JSH_ANALOG_CH8, { JSH_AF0|JSH_TIMER3|JSH_TIMER_CH3, JSH_AF1|JSH_TIMER1|JSH_TIMER_CH2|JSH_TIMER_NEGATED, JSH_AF0|JSH_TIMER8|JSH_TIMER_CH2|JSH_TIMER_NEGATED, 0 } },
/* PB1  */ { JSH_PORTB, JSH_PIN1, JSH_ANALOG12|JSH_ANALOG_CH9, { JSH_AF0|JSH_TIMER8|JSH_TIMER_CH3|JSH_TIMER_NEGATED, JSH_AF1|JSH_TIMER1|JSH_TIMER_CH3|JSH_TIMER_NEGATED, JSH_AF0|JSH_TIMER3|JSH_TIMER_CH4, 0 } },
/* PB2  */ { JSH_PORTB, JSH_PIN2, JSH_ANALOG_NONE, { 0, 0, 0, 0 } },
/* PB3  */ { JSH_PORTB, JSH_PIN3, JSH_ANALOG_NONE, { JSH_AF1|JSH_TIMER2|JSH_TIMER_CH2, JSH_AF1|JSH_SPI1|JSH_SPI_SCK, JSH_AF0|JSH_SPI3|JSH_SPI_SCK, 0 } },
/* PB4  */ { JSH_PORTB, JSH_PIN4, JSH_ANALOG_NONE, { JSH_AF1|JSH_TIMER3|JSH_TIMER_CH1, JSH_AF0|JSH_SPI3|JSH_SPI_MISO, JSH_AF1|JSH_SPI1|JSH_SPI_MISO, 0 } },
/* PB5  */ { JSH_PORTB, JSH_PIN5, JSH_ANALOG_NONE, { JSH_AF0|JSH_SPI3|JSH_SPI_MOSI, JSH_AF1|JSH_SPI1|JSH_SPI_MOSI, JSH_AF1|JSH_TIMER3|JSH_TIMER_CH2, 0 } },
/* PB6  */ { JSH_PORTB, JSH_PIN6, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER4|JSH_TIMER_CH1, JSH_AF1|JSH_USART1|JSH_USART_TX, JSH_AF0|JSH_I2C1|JSH_I2C_SCL, 0 } },
/* PB7  */ { JSH_PORTB, JSH_PIN7, JSH_ANALOG_NONE, { JSH_AF1|JSH_USART1|JSH_USART_RX, JSH_AF0|JSH_I2C1|JSH_I2C_SDA, JSH_AF0|JSH_TIMER4|JSH_TIMER_CH2, 0 } },
/* PB8  */ { JSH_PORTB, JSH_PIN8, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER4|JSH_TIMER_CH3, JSH_AF1|JSH_I2C1|JSH_I2C_SCL, 0, 0 } },
/* PB9  */ { JSH_PORTB, JSH_PIN9, JSH_ANALOG_NONE, { JSH_AF1|JSH_I2C1|JSH_I2C_SDA, JSH_AF0|JSH_TIMER4|JSH_TIMER_CH4, 0, 0 } },
/* PB10 */ { JSH_PORTB, JSH_PIN10, JSH_ANALOG_NONE, { JSH_AF1|JSH_TIMER2|JSH_TIMER_CH3, JSH_AF0|JSH_USART3|JSH_USART_TX, JSH_AF0|JSH_I2C2|JSH_I2C_SCL, 0 } },
/* PB11 */ { JSH_PORTB, JSH_PIN11, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART3|JSH_USART_RX, JSH_AF0|JSH_I2C2|JSH_I2C_SDA, JSH_AF1|JSH_TIMER2|JSH_TIMER_CH4, 0 } },
/* PB12 */ { JSH_PORTB, JSH_PIN12, JSH_ANALOG_NONE, { 0, 0, 0, 0 } },
/* PB13 */ { JSH_PORTB, JSH_PIN13, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER1|JSH_TIMER_CH1|JSH_TIMER_NEGATED, JSH_AF0|JSH_SPI2|JSH_SPI_SCK, 0, 0 } },
/* PB14 */ { JSH_PORTB, JSH_PIN14, JSH_ANALOG_NONE, { JSH_AF0|JSH_SPI2|JSH_SPI_MISO, JSH_AF0|JSH_TIMER1|JSH_TIMER_CH2|JSH_TIMER_NEGATED, 0, 0 } },
/* PB15 */ { JSH_PORTB, JSH_PIN15, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER1|JSH_TIMER_CH3|JSH_TIMER_NEGATED, JSH_AF0|JSH_SPI2|JSH_SPI_MOSI, 0, 0 } },
/* PC0  */ { JSH_PORTC, JSH_PIN0, JSH_ANALOG123|JSH_ANALOG_CH10, { 0, 0, 0, 0 } },
/* PC1  */ { JSH_PORTC, JSH_PIN1, JSH_ANALOG123|JSH_ANALOG_CH11, { 0, 0, 0, 0 } },
/* PC2  */ { JSH_PORTC, JSH_PIN2, JSH_ANALOG123|JSH_ANALOG_CH12, { 0, 0, 0, 0 } },
/* PC3  */ { JSH_PORTC, JSH_PIN3, JSH_ANALOG123|JSH_ANALOG_CH13, { 0, 0, 0, 0 } },
/* PC4  */ { JSH_PORTC, JSH_PIN4, JSH_ANALOG12|JSH_ANALOG_CH14, { 0, 0, 0, 0 } },
/* PC5  */ { JSH_PORTC, JSH_PIN5, JSH_ANALOG12|JSH_ANALOG_CH15, { 0, 0, 0, 0 } },
/* PC6  */ { JSH_PORTC, JSH_PIN6, JSH_ANALOG_NONE, { JSH_AF1|JSH_TIMER3|JSH_TIMER_CH1, JSH_AF0|JSH_TIMER8|JSH_TIMER_CH1, 0, 0 } },
/* PC7  */ { JSH_PORTC, JSH_PIN7, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER8|JSH_TIMER_CH2, JSH_AF1|JSH_TIMER3|JSH_TIMER_CH2, 0, 0 } },
/* PC8  */ { JSH_PORTC, JSH_PIN8, JSH_ANALOG_NONE, { JSH_AF1|JSH_TIMER3|JSH_TIMER_CH3, JSH_AF0|JSH_TIMER8|JSH_TIMER_CH3, 0, 0 } },
/* PC9  */ { JSH_PORTC, JSH_PIN9, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER8|JSH_TIMER_CH4, JSH_AF1|JSH_TIMER3|JSH_TIMER_CH4, 0, 0 } },
/* PC10 */ { JSH_PORTC, JSH_PIN10, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART4|JSH_USART_TX, JSH_AF1|JSH_USART3|JSH_USART_TX, 0, 0 } },
/* PC11 */ { JSH_PORTC, JSH_PIN11, JSH_ANALOG_NONE, { JSH_AF1|JSH_USART3|JSH_USART_RX, JSH_AF0|JSH_USART4|JSH_USART_RX, 0, 0 } },
/* PC12 */ { JSH_PORTC, JSH_PIN12, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART5|JSH_USART_TX, 0, 0, 0 } },
/* PC13 */ { JSH_PORTC, JSH_PIN13, JSH_ANALOG_NONE, { 0, 0, 0, 0 } },
/* PC14 */ { JSH_PORTC, JSH_PIN14, JSH_ANALOG_NONE, { 0, 0, 0, 0 } },
/* PC15 */ { JSH_PORTC, JSH_PIN15, JSH_ANALOG_NONE, { 0, 0, 0, 0 } },
/* PD0  */ { JSH_PORTD, JSH_PIN0, JSH_ANALOG_NONE, { 0, 0, 0, 0 } },
/* PD1  */ { JSH_PORTD, JSH_PIN1, JSH_ANALOG_NONE, { 0, 0, 0, 0 } },
/* PD2  */ { JSH_PORTD, JSH_PIN2, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART5|JSH_USART_RX, 0, 0, 0 } },

So that would seem to back up what you're saying about what timers are chosen... The order (I think) just comes from the order that they're defined in the CSV file (that has been grabbed from the STM32F1 datasheet).

So I guess simply ordering the PWM timers lowest to highest for each pin would really help - although the smartest solution is probably to prioritise the timer that isn't used for anything else.