Could the Espruino be made into an I2C slave device?

If so, how could this be done? Code examples?
Since there will be a lower cost Espruino/Espruini coming out, it would be nice if multiple Espruinos could be linked together with two wires.

Interesting idea... I think things like SPI/I2C slaves are a bit tricky because you basically need an instant reply when data is requested. Something could be added in native code I guess, or if we could think of a nice way to expose it as an API then slave support could definitely be done.

Probably the easiest way to connect them together is to use serial though - I can think of two pretty easy ways:

• chain RX to TX along all the different boards
  
• have a single wire, pulled to 3.3v with a resistor - then connect ALL RX and TX lines together and set RX to 'input' and TX to 'output_opendrain' - then every board can send messages to every other board, using a single wire.
  

Something could be added in native code I guess, or if we could think
of a nice way to expose it as an API then slave support could
definitely be done.

Perfect, if it could be done.

Our programs are so large that if we could multi-process between Espruinos it would be a great help.

The STM supports a special Half duplex mode in the UART see section 27.3.10 in the reference manual, this would save you a port line. Also this might stop you receiving what you transmit.

Single-wire half-duplex communication
The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
• LINEN and CLKEN bits in the USART_CR2 register,
• SCEN and IREN bits in the USART_CR3 register.

The USART can be configured to follow a single-wire half-duplex protocol. In single-wire
half-duplex mode, the TX and RX pins are connected internally. The selection between halfand
full-duplex communication is made with a control bit ‘HALF DUPLEX SEL’ (HDSEL in
USART_CR3).
As soon as HDSEL is written to 1:
• RX is no longer used,
• TX is always released when no data is transmitted. Thus, it acts as a standard IO in idle
or in reception. It means that the IO must be configured so that TX is configured as
floating input (or output high open-drain) when not driven by the USART.
Apart from this, the communications are similar to what is done in normal USART mode.
The conflicts on the line must be managed by the software (by the use of a centralized
arbiter, for instance). In particular, the transmission is never blocked by hardware and
continue to occur as soon as a data is written in the data register while the TE bit is set.

Sounds good - it's pretty easy to flip that bit using the peek and poke instructions if you want to give it a try!