I see no real advantage in having it at address 0. I would see it 'easy to understand' if it would not conflict with any existing memory.
The address map of RPI2040 is here - Chapter 2.2. Address Map https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#page=25
ROM | 0x00000000 XIP | 0x10000000 SRAM | 0x20000000 APB Peripherals | 0x40000000 AHB-Lite Peripherals | 0x50000000 IOPORT Registers | 0xd0000000 Cortex-M0+ internal registers | 0xe0000000
nrf52 has spi flash at virtual 0x60000000 because it does not conflict with anything there too
And BTW thanks for picking it up, maybe @ndabas could share his attempt mentioned here http://forum.espruino.com/conversations/359042/#15983946
@fanoush started
Espruino is a JavaScript interpreter for low-power Microcontrollers. This site is both a support community for Espruino and a place to share what you are working on.
I see no real advantage in having it at address 0. I would see it 'easy to understand' if it would not conflict with any existing memory.
The address map of RPI2040 is here - Chapter 2.2. Address Map
https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#page=25
ROM | 0x00000000
XIP | 0x10000000
SRAM | 0x20000000
APB Peripherals | 0x40000000
AHB-Lite Peripherals | 0x50000000
IOPORT Registers | 0xd0000000
Cortex-M0+ internal registers | 0xe0000000
nrf52 has spi flash at virtual 0x60000000 because it does not conflict with anything there too
And BTW thanks for picking it up, maybe @ndabas could share his attempt mentioned here http://forum.espruino.com/conversations/359042/#15983946