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@fanoush
Well, different CS pin should be all that is needed, that is how SPI works. Without CS selected spi slaves should ignore everything. So hopefully with stacked chips on top like this even the dual and quad SPI that reuses WP and HOLD pins for data i/o should work as long as CS is properly used. At least it is mentioned here https://embeddedinventor.com/quad-spi-everything-you-need-to-know/ near the end - "multiple devices can be linked to a single Quad-SPI interface and the same data lines can be connected to multiple devices. To select a particular chip, the chip select pin can be used. "
Maybe that is even how it works with SPI flash and SPI SRAM on ESP32 now - flash and sram is on same SPI bus. EDIT: yes, documented here