Logically invert the pin?

Thr 2018.11.15

Two topics have resulted:

Topic 1

'You're on STM32?'

In #21

'my own board ... custom build ... Nothing special, ... based on STM32Discovery'

Is it reasonable to infer that there are 5v tolerant pins? (are these the correct docs?)

"Up to 136 fast I/Os, most 5 V-tolerant"
from bullet list
https://www.st.com/en/microcontrollers/s­tm32l496ag.html
from link
http://www.espruino.com/STM32L496GDISCOV­ERY

Topic 2

Thank you @George for cut-n-paste-n-post of the image #30. (From #17 link WS2812)

I'm going out on a limb here, but I owe it to George as I may have mis-led on our lengthy exchange (#17-#25) we had two weeks ago on Sun Nov 04 as we may be in near adjacent time zones. (I'm in CST six hours behind Gordon GMT, allObjects PST - how about George?)

Out on the branch,

I jumped (#17) into this thread after a several day exchange head start and without a scope to confirm some hunches. George has done exhaustive testing and made many trial attempts at a software resolution. I had a hunch from flicker I had seen using the Neopixel during a separate code project I was working on. I made (wrongly) a suggestion, which George coded and attempted, while I patiently waited his reply.

Further out,

After many hours of re-reading the data sheets and re-thinking on the porcelain goddess, I believe I uncovered the why as to why inverting the bit stream most likely wont work. We are (speaking for George here, I believe he'll agree) in agreement that the suggestion of inverting the output using @Gordon #31 suggestion af_opendrain will (and does) invert the data at the pin.

Further out and the limb is really bending here,

But inverting the data isn't the issue. Please re-read my #18 explanation as I believe George agrees from his #21 & #23 response, that I discovered the real issue is with the (polarity and when) of the latch pulse needed by the 5050, as described by the learn.adafruit article from #18.

Really out there,

Unless one has a much faster clock rate and a whole bunch of code to create a false latch pulse leading edge, (which I'm not entirely convinced,
would allow for a sync'd pattern within the data) then simulate equivalent widths of inverted data, after the 50usec delay, inverting the data wont solve the demand of the 5050 hardware.

Ready to take a bullet,

Maybe @allObjects or @MaBe will catch this entry, @George are you there?, this evening to be able to add some insight before @Gordon will view this early Fri am.