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  • Yesss, that's cut it almost in half, now it's only 139 ns. Are there still wait states for other reasons?

    Thanks!

    
    //STM32F103RCT6.pdf -> https://www.st.com/resource/en/reference­_manual/cd00171190.pdf
    //7.3.2 Clock configuration register (RCC_CFGR)
    //Read RCC_CFGR (see section 7.3.2)
    var a=peek32(0x40021004).toString(2);
    while (a.length<32) a="0"+ a;
    a
    00000000000111010010110000001010
    
    00000 000 0 0 0111 0 1 00 101 100 0000 10 10
    
    RESERVED: 00000
    MCO:        000 -> no clock (Microcontroller clock output)
    RESERVED:     0
    USBPRE:       0 -> PLL clock is divided by 1.5 (USB prescaler)
    PLLMUL:    0111 -> clk*9 (PLL multiplication factor)
    PLLXTPRE:     0 -> HSE clock not divided (HSE divider for PLL entry)
    PLLSRC:       1 -> Clock from PREDIV1 selected as PLL input clock
    ADCPRE:      00 -> PCLK2 divided by 2 (ADC prescaler)
    PPRE2:      101 -> HCLK divided by 4 (APB high-speed prescaler(APB2))
    PPRE1:      100 -> HCLK divided by 2 (APB Low-speed prescaler(APB1))
    HPRE:      0000 -> SYSCLK not divided (AHB prescaler)
    SWS:         10 -> PLL used as system clock
    SW:          10 -> PLL selected as system clock
    */
    
    //Put 000 into PPRE2
    poke32(0x40021004,peek32(0x40021004)&~(7­<<11));
    
    

    1 Attachment

    • fast_gpio.jpg
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