• The thing I worked on did both actually - it'd create HDL based on the code you provided, and would make opcodes for that special soft core, but in a relatively optimised way.

    It gave a neat little report of all the ALUs and their usage each clock cycle, and then you could use macros to give the compiler hints, like 'do this add on that adder unit'.

    ... so it effectively let you design the processor and a VLIW code in parallel. As I understood it, it made it into Altera's set of tools soon after I left - but it's been 10 years since so I have no idea what's happened to it now!


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